Verification of HW functionalities of core Packet Processing blocks in networking chips
Architect and Create verification environments using Systemverilog and Universal verification methodology-UVM.
In-depth understanding of HW and architectural implementation to enable solving of complex problems.
Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results.
Ability to communicate effectively to work with cross-functional and cross-design centers.
Work with designers, architects, software and other crosss-functional teams to refine definition and build solutions
Escalation point for complex issues
Experience: Typically requires a minimum of 8 years of related experience. At this level, post-graduate coursework may be desirable.
Salary: Not Disclosed by Recruiter
Industry: Semiconductors / Electronics
Functional Area: Engineering Design, R&D
Role Category: Engineering
Role: Senior Design Engineer
Employment Type: Permanent Job, Full Time